The invention concerns a switching arrangement for establishing any one of a plurality of selectable signal paths between a corresponding plurality of first ports and a common port and for varying the attenuation of at least one of the selectable signal paths.
Circuits are known which allow the establishing of a signal path between any one of a number of first ports and a second, common port and which also allow the signal flowing along that path to experience a desired degree of attenuation.
FIG. 1 shows such a known arrangement in the form of an SPDT (single-pole, double-throw) switch and comprises two first ports 11 and 12 and a second, common port 13. Two FETs 14 and 15 act as port-select elements for establishing, as required, a signal path between a selected one of the ports 11 and 12 and the common port 13. If required, a further FET 16 may be included to provide a shunt path for enhanced isolation of port 12 from the common port 13 when FET 15 is switched into non-conducting mode. Port selection is achieved by the application of control signals C and C on the gates of FETs 14, 15 and 16, FETs 14 and 16 being driven in antiphase to FET 15. One of the first ports, 11, has included in the signal path an attenuating means 17 which comprises a resistive network 18 and two attenuation switching elements in the form of FET switches 19 and 20. The switches 19 and 20 are controlled in antiphase at their gates via control signals P and P, respectively, such that, when P is zero volts and P is, say, -5 V, FET 19 forms a through-path of low impedance for the signal on port 11, while FET 20 is switched into a non-conductive state to remove any loading effect of the network 18 on the incoming signal, especially at the downstream end of the FET 19.
In contrast, when P is set to -5 V and P is set to 0 V, the signal path includes the unshunted network 18 and the signal on port 11 is therefore attenuated when it reaches port 13.
The two functions of attenuation and port selection are completely independent in this arrangement, such that any setting of the attenuation means 17 will be rendered ineffective until such time as FET 14 is switched into conduction. This occurs by the application of a zero-volt level on its gate (and on the gate of FET 16, as required), FET 15 being at the same time rendered non-conductive with the application of a -5 V signal on its gate.
This known arrangement has the drawback that when port 11 is selected and the attenuation is set to nominally zero by the placing of a zero-volt signal on the gate of FET 19, the signal path from port 11 to the common port 13 contains two series-connected FET ON-impedances associated with FETs 19 and 14, as opposed to only one such impedance (that associated with FET 15) in the signal path from port 12 to port 13. This gives rise to a higher absolute value of series resistance in the series path than may be desirable for the "zero-attenuation" state. In addition, there may be a significant imbalance between the amplitude of the two signals selectively fed to the common port 13, though this depends on the magnitude of losses which may occur elsewhere in the signal paths.
It is desirable to provide a switching arrangement which overcomes or mitigates the above drawbacks of the known arrangement.